Anti-fuses and fuses have been commonly used in the semiconductor industry for one-time programming purposes. They can be used to repair dynamic random access memory (DRAM) arrays by swapping defective cells with redundant cells. They can also be used in various products for configuration, updating and repairing. Anti-fuse structures typically include a material which initially has a very high resistance but after programming by an electrical or optical means is converted to a lower resistance state. Programming refers to the process of selectively blowing fuses and/or causing selected anti-fuses to become conductive.
FIG. 1 schematically illustrates a cross section of a prior art anti-fuse structure 10, which includes a metal-1 layer 14, an anti-fuse layer 16, and an interconnect layer 22 embedded in a dielectric layer 18. Interconnect layer 22 is formed in via 20 through layer 18. During programming, an appropriate voltage between metal-1 layer 14 and interconnect layer 22 is applied to create a conductive path, i.e., resistance of the anti-fuse structure is lowered after the programming.
Processing for integrating the anti-fuse structures mentioned above requires at least one extra masking and etching step, which increases overall fabrication costs. Further, since the programming voltage for creating the electrical path is a function of the thickness of the anti-fuse layer 16, the anti-fuse material can be damaged by dielectric over-etch or under-etch, which could lead to programming failure, i.e., the electrical path would not be properly formed when an appropriate voltage is applied. Most of the existing anti-fuse structure have a layer of anti-fuse material sandwiched in between two “disconnected” conductive materials. This requirement not only limits the design flexibility and enlarges the area required for forming the element, but also requires high programming voltage to break the anti-fuse layer during programming.
U.S. Pat. No. 5,789,795 entitled “Methods and apparatus for fabricating anti-fuse devices,” granted Aug. 4, 1998 to Sanchez et al., teaches an etch stop layer disposed above an anti-fuse layer, and an inter-metal oxide layer disposed above the etch layer, with the oxide layer having a via formed therein. U.S. Pat. No. 6,335,228 entitled “Method for making an anti-fuse,” granted Jan. 1, 2002 to Fuller et al., teaches a process for producing DRAMs having redundant components, including steps for concurrently forming normal contacts and anti-fused contacts. U.S. Pat. No. 6,251,710 entitled “Method of making a dual damascene anti-fuse with via before wire,” granted Jun. 26, 2001 to Radens et al., teaches an anti-fuse structure which includes: a substrate having a first level of electrically conductive features; a patterned anti-fuse material; a patterned interlevel dielectric material; and a second level of electrically conductive features.
U.S. Pat. No. 6,124,194 entitled “Methods of fabrication of anti-fuse integrated with dual damascene process,” granted Sep. 26, 2000 to Shao et al., teaches an anti-fuse process which uses a SiN layer to pattern at least two openings. The first opening exposes the metal via, and the second opening exposes a portion of the first dielectric layer above the second metal line. U.S. Pat. No. 5,903,041, entitled “Integrated Two-Terminal Fuse-Antifuse and Fuse and Integrated Two-Terminal Fuse-Antifuse Structures Incorporating an Air Gap,” was granted May 11, 1999 to LaFleur et al. In the La Fleur design, air gaps are presented above and below the fuse element. The fuse and antifuse are operated in a mutually exclusive manner. First, high voltage is built up across the antifuse to cause it to short. Then, the fuse is blown open via a high level of current flow. Fuse material is not used to short the antifuse. High programming voltage levels are required to program the antifuse.
Further improvements in prior art approaches are desirable.